Generally, the present disclosure relates to semiconductor devices, and, more specifically, to various novel resistive nonvolatile memory cells with shared access transistors and methods of operating the resistive nonvolatile memory cells.
A resistive memory cell may store information by changing the electrical resistance of a non-volatile memory device, for example, a magnetic tunnel junction (MTJ) element. The MTJ element typically includes a thin insulating tunnel barrier layer sandwiched between a magnetically fixed layer and a magnetically free layer, forming a magnetic tunnel junction. Magnetic orientations of the fixed and free layers may be perpendicular to the growth direction, forming a perpendicular MTJ (or pMTJ) element.
Spin transfer torque (STT) or spin transfer switching, uses spin-aligned (“polarized”) electrons to directly apply a torque on the MTJ layers. Specifically, when electrons flowing into a layer have to change spin direction, a torque is developed and is transferred to the nearby layer. The resistance of the MTJ element changes when the spin direction of that layer changes. Other examples of such resistive non-volatile memory devices include memristors (used in ReRAMs) and phase-change (PC) materials (used in PC-RAMs).
Resistive memory cells are typically provided as addressable bit cells in an array of columns and rows. Such an array is provided with corresponding source lines, bit lines and word lines to perform operations on selected bit cells. Typically, each column of memory cells is provided with a dedicated source line and a dedicated bit line. As technology scales, there is difficulty in reducing the amount of chip area and height used by such memory cell arrays. Tis is due to the fact that a relatively large current is required to write into a resistive memory cell to provide the desired current for it to switch from one state to the other. For example, for an MTJ element, a minimum current is required to produce enough torque to switch the magnetic orientation of the cell. The access transistor for writing to the resistive memory cell is sized according to these current demands, which limits the scalability of the cell layout.